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SC7312
4-CH OUTPUT STEREO AUDIO PROCESSOR WITH 4 STEREO INPUTS AND TONE/VOLUME CONTROL
DESCRIPTION
The SC7312 is a volume, tone (bass and treble), balance (left/ right) and fader(front/rear) processor for quality audio applications in car radio and Hi-Fi systems. Selectable input gain and external loudness function are provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal settings is obtained by resistor networks and switches combined with operational amplifiers. Due to the Used CMOS technology, low distortion, low noise and low DC stepping are obtained.
SOP-32-375-1.27
FEATURES
* Input multiplexer: --4 stereo inputs --Selectable input gain for optimal adaptation to different sources * Four speaker attenuators: --4 independent speakers control in 1.25dB steps for balance and fader facilities --Independent mute function * All functions programmable via serial I 2C Bus * Loudness function * Volume control in 1.25dB steps * Treble and bass control * Input and output for external equalizer or noise reduction system
ORDERING INFORMATION
Device SC7312S Package SOP-32-375-1.27
BLOCK DIAGRAM
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SC7312
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltages Operating Temperature Storage Temperature Symbol VS Tamb Tstg Ratings 10.2 -40 ~ +85 -55 ~ +150 Unit V C C
QUICK REFERENCE DATA
Characteristics Supply Voltage Maximum Input Signal Handling Total Harmonic Distortion ,V=1Vrms, f=1kHz Signal to Noise Ratio Channel Separation, f=1kHz Volume Control, 1.25dB step Bass and Treble Control, 2dB step Fader and Balance Control, 1.25dB step Input Gain, 3.75dB Step Mute Attenuation 0 100 11.25 dB dB S/N Sc -78.75 -14 -38.75 106 103 0 +14 0 dB dB dB dB dB Symbol Vs VCL THD Min. 6 2 0.01 0.1 Typ. 9 Max. 10 Unit V Vrms %
ELECTRICAL CHARACTERISTICS (Refer to the test circuit)
(Tamb=25C, VS=9.0V, RL=10k, RG=600, all controls flat(G=0), f=1kHz,Unless otherwise specified) Characteristics SUPPLY VOLTAGE www..com Operating Supply Voltage Operating Supply Current Ripple Rejection of Supply Voltage INPUTS SELECTORS Input Resistance Clipping Level Input Separation (note 2) Output Load Resistance Minimum Input Gain Maximum Input gain Step Resolution Input Noise DC Steps RII VCL SIN RL GIN(MIN) GIN(MAX) GSTEP eIN VDC G=11.25dB Adjacent gain steps G=18.75 to MUTE Pin 8, 21 Input 1, 2, 3, 4 35 2 80 4 -1 0 11.25 3.75 2 4 4 20 1 50 2.5 100 70 k Vrms dB k dB dB dB V mV mV
(To be continued)
Symbol VS IS SVR
Test conditions
Min. 6
Typ. 9 20.0
Max. 10.0 35.0
Unit V mA dB
60
80
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SC7312
(Continued)
Characteristics VOLUME CONTROL Input Resistance Control Range Minimum Attenuation Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps SPEAKER ATTENUATORS Control Range Step Resolution Attenuation Set Error Output Mute Attenuation DC Steps BASS CONTROL (note 1) Control Range Step Resolution Internal Feedback Resistance TREBLE CONTROL (note 1) Control Range
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Symbol RIV Crange AV(min) AV(max) ASTEP EA ET VDC
Test conditions
Min. 20 70 -1 70 0.5
Typ. 33 75 0 75 1.25 0
Max. 50 80 1 80 1.75 1.25 2 2
Unit k dB dB dB dB dB dB mV mV
AV=0 to -20dB AV=-20 to -60dB
-1.25 -3
Adjacent attenuation steps From 0dB to AV max
0 0.5
3 7.5
Crange SSTEP EA AMUTE VDC Adjacent attenuation steps From 0dB to MUTE
35 0.5
37.5 1.25
40 1.75 1.5
dB dB dB dB
80
100 0 1 3 10 16 3 58 15 3
mV mV
GB BSTEP RB
Maximum boost/cut
12 1 34 13 1
14 2 44 14 2
dB dB k
Gt TSTEP
Maximum boost/cut
dB dB
Step Resolution AUDIO OUTPUTS Clipping Level Output Load Resistance Output load Capacitance Output Resistance DC Voltage Level GENERAL
VOCL RL CL ROUT VOUT
THD=0.3%
2 4
2.5
Vrms k 10 nF V V 15 V V dB
(To be continued)
30 4.2
75 4.5
120 4.8
BW=20 ~20kHz,flat output muted Output Noise eNO BW=20 ~20kHz,flat All gains=0dB A curve, all gains =0 dB Signal to Noise Ratio S/N All gains=0dB; Vo=1Vrms
2.5 5 3 106
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SC7312
(Continued)
Characteristics Distortion
Symbol d
Test conditions Av=0,VIN=10mV Av=-20dB, VIN=1Vrms Av=-20dB,VIN=0.3Vrms
Min.
Typ. 0.01 0.09 0.04
Max. 0.1 0.3
Unit % % % dB
Channel Separation Left/right Total Tracking Error BUS INPUTS Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge NOTES:
Sc AV=0 to - dB 20 AV=-20 to -60 dB
80
103 0 0 1 2
dB dB
VIL VIH IIN Vo IO=1.6mA 3 -5
1
V V A V
+5 0.4
(1) Bass and treble response see Figure 16. The center frequency and quality of the response behavior can be chosen by the external circuitry. A standard first order bass response can realized by a standard feedback network. (2) The selected input is grounded through the 2.2F capacitor.
PIN CONFIGURATIONS
CREF VDD GND CODE
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1 2 3 4 5 6 7
32 SCL 31 SDA 30 DIG GND 29 OUT LF 28 OUT RF 27 OUT LR 26 OUT RR
BUS INPUTS
L TREBLE R IN(R) OUT(R) LOUD R
SC7312
8 9
25 BOUT(R) 24 BIN(R)
BASS
23 BOUT(L) 22 BIN(L) 21 OUT(L) 20 IN(L) 19 L1 18 L2 17 L3
R4 10 RIGHT INPUTS R3 11 R2 12 R1 13 NC 14 LOUD L 15 LEFT INPUTS -- L4 16
LEFT INPUTS
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SC7312
TYPICAL CHARACTERISTICS PERFORMANCE
Loudness (dB)
Loudness (dB)
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Channel Separation (dB) THD & Noise (%)
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THD (%)
THD & Noise (%)
Noise ( V)
Noise ( V)
Loudness (dB)
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SC7312
TYPICAL CHARACTERISTICS PERFORMANCE (continued)
Fig.10 Input Separation ( L1,L2,L3,L4) vs. Frequency
110 100
Fig.11 Supply Voltage Rejection vs. Frequency
Fig.12 Output Clipping Level vs. Supply Voltage
Channel Separation (dB)
Channel Separation (dB)
90
Output Clipping Level (v)
5.0 RL=10k f=1kHz THD=0.3% 4.0
100
80
90
VIN=1Vrms AV=0dB All controls Flat
70 Vsvr=0.5Vrms All Input to GND AV=0dB All controls Flat
3.0
80
60
2.0
70 1.0 1 10 2 10 3 10 4 10 1 10 2 10 3 10 4 10 4 6 8 10 12
Frequency (Hz)
Frequency (Hz)
Supply Voltage (V)
Fig.13 Quiescent current vs. Supply Voltage
9.0
Fig.14 Supply current vs. Temperature
50
Fig.15 Bass resistance vs. Temperature
Quiescent Current (mA)
Quiescent Current (mA)
8.5
48
8.0
8.0 Vs=9V
Bass Resistance (
30 60 90
)
46 7.5 44 7.0 42 6.5 40 -60 -30 0 -60 -30 0 30 60 90
6.0
4.0
2.0 4 6 8 10 12
Supply Voltage (V)
Temperature ( )
Temperature (
)
Fig.16 Typical Tone Response (with the Ext components indicated the test circuit)
15 AV=0dB 10
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Tone Response (dB)
5
0
-5
-10
-15 1 10 2 10 3 10 4 10
Frequency (Hz)
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SC7312
APPLICATION NOTES
1. I2C BUS INTERFACE Data transmission from microprocessor to the SC7312 and viceversa takes place through the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be connected). 2. DATA VALIDITY As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the dtat line can only change when the clock signal on the SCL line is LOW.
Fig. 17 Data Validity on the I2C BUS
3. START AND STOP CONDITIONS As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
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Fig. 18 Timing diagram of I2C BUS
4. BYTE FORMAT Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge bit. The MSB is transferred first. 5. ACKNOWLEDGE The master(microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse(see Figure 19). The peripheral(audioprocessor) that acknowledges has to pull-down(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte , otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
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SC7312
Fig. 19 Acknowledge on the I2C BUS 6. Transmission without acknowledge Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission: simply it waits one clock without checking the slave acknowledgig, and sends the new data. This approach of course is less protected from mis-working and decreases the noise immunity.
SOFTWARE SPECIFICATION
1. Interface protocol The interface protocol comprises:
* * * *
A start conditions A chip address byte, containing the SC7312 address(the 8th bit of the bytes must be 0). The SC7312 must always acknowledge at the end of each transmitted byte. A sequence of data(N-bytes + acknowledge) A stop condition (P)
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2. Chips address 1 (MSB) 3. Data bytes MSB 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 G1 0 1 B0 B0 B0 B0 B0 G0 C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 A1 A1 A1 A1 A1 S1 C1 C1 LSB A0 A0 A0 A0 A0 S0 C0 C0 Volume Control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control Function 0 0 0 1 0 0 0 (LSB)
Note: Ax=1.25dB steps;Bx=10dB steps;Cx=2dB steps;Gx=3.75dB steps
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SC7312
DETAILED DESCRIPTION OF DATA BYTES
1. Volume MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 Function Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70
For example, a volume of -45dB is given by: 00100100 2. speaker attenuators MSB 1 1 1 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1
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LSB A0 A0 A0 A0 0 1 0 1 0 1 0 1 Speaker ATT LF Speaker ATT RF Speaker ATT LR
Function
Speaker ATT RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 MUTE
For example, attenuation of 25dB on speaker RF is given by: 10110100
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SC7312
3.Audio switch MSB 0 1 0 G1 G0 S2 S1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 LSB S0 0 1 0 1 Function Audio switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 Loudness ON Loudness OFF +11.25dB +7.5dB +3.75dB 0dB
For example, to select the stereo 2 input with a gain of +7.5dB Loudness ON the 8bit string is: 01001001 4.Bass and treble MSB 0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0
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LSB C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Function Bass Terble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
0 1 1 1 1 1 1 1 1
C3=Sign For Example, bass at - 10dB is obtained by the following 8bit string is: 01100010.
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SC7312
TEST AND TYPICAL APPLICATION CIRCUIT
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SC7312
PACKAGE OUTLINE
SOP-32-375-1.27 UNIT: mm
20.980.10
2.54MAX
0.150.05
1.27
0.40
0.250.05
19.05
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HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken: * Persons at a work bench should be earthed via a wrist strap. * Equipment cases should be earthed. * All tools used during assembly, including soldering tools and solder baths, must be earthed. * MOS devices should be packed for dispatch in antistatic/conductive containers.
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